M32C80 Datasheet, PDF (207/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O (UART)
16.2.2 Selecting LSB First or MSB First
As shown in Figure 16.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format.
This function is available for 8-bit transfer data.
(1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first)
CLKi ^"H"
"L"
TxDi ^"H"
"L"
"H"
RxDi _"L"
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first)
CLKi ^"H"
"L"
TxDi ^"H"
"L"
RxDi
"H"
"L"
ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
transmitted on the falling edge of the transfer clock and received on the rising edge)
and the UiLCH bit in the UiC1 register is set to "0" (no inverse).
ST: Start bit
P: Parity bit
SP: Stop bit
Figure 16.16 Transfer Format
16.2.3 Serial Data Logic Inverse
When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB
register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB
register. Figure 16.17 shows a switching example of the serial data logic.
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (no inverse)
Transfer Clock ^"H"
"L"
TxDi "H"
(no inverse) _"L"
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
Transfer Clock ^"H"
"L"
TxDi "H"
(inverse) _"L"
ST _{D0 D1 D2 D3 D4 D5 D6 D7}
P SP
NOTE:
1. The above applies when the UFORM bit in the UiC0 register is set to "0" (
LSB first), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the
PRYE bit is set to "1" (parity enabled).
ST: Start bit
P: Parity bit
SP: Stop bit
Figure 16.17 Serial Data Logic Inverse
Rev. 1.00 Nov. 01, 2005 Page 188 of 330
REJ09B0271-0100