M32C80 Datasheet, PDF (160/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
14. Timer (Timer A)
14.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing
Z-phase input resets the timer counter when processing a two-phase pulse signal.
This function can be used in timer A3 event counter mode, two-phase pulse signal processing, free-
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running count operation type or multiply-by-4 processing. The Z-phase signal is applied to the INT2 pin.
When the TAZIE bit in the ONSF register is set to "1" (Z-phase input enabled), Z-phase input can
reset the timer counter. To reset the counter by a Z-phase input, set the TA3 register to "000016"
beforehand.
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Z-phase input is enabled when the edge of the signal applied to the INT2 pin is detected. The POL bit
in the INT2IC register can determine edge polarity. The Z-phase must have a pulse width of one timer
A3 count source cycle or more . Figure 14.10 shows two-phase pulses (A-phase and B-phase) and
the Z-phase.
Z-phase input resets the timer counter in the next count source following Z-phase input. Figure 14.11
shows the counter reset timing.
Timer A3 interrupt request is generated twice continuously when a timer A3 overflow or underflow,
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and a counter reset by INT2 input occur at the same time. Do not use the timer A3 interrupt request
when this function is used.
TA3OUT
(A-phase)
TA3IN
(B-phase)
Count source
INT2 ⁽¹⁾
(Z-phase)
Pulse width of one count source cycle
or more is required
NOTE:
1. When the rising edge of INT2 is selected.
Figure 14.10 Two-Phase Pulse (A-phase and B-phase) and Z-phase
TA3OUT
(A-phase)
TA3IN
(B-phase)
Count source
INT2 ⁽¹⁾
(Z-phase)
Counter value
m m+1 1
2
3
4
5
Timer counter is reset NOTE:
at this timing
1. When the rising edge of INT2 is selected.
Figure 14.11 Counter Reset Timing
Rev. 1.00 Nov. 01, 2005 Page 141 of 330
REJ09B0271-0100