M32C80 Datasheet, PDF (275/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
21. Intelligent I/O (Communication Function)
21.1.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1)
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. f8 or f2n
can be selected as the transfer clock.
Table 21.2 lists specifications of clock synchronous serial I/O mode for the communication units 0 and 1.
Tables 21.3 and 21.4 list clock settings. Table 21.5 lists register settings. Tables 21.6 and 21.7 list pin
settings. Figure 21.12 shows an example of transmit and receive operation.
Table 21.2 Clock Synchronous Serial I/O Mode Specifications (Communication Units 0 and 1)
Item
Specification
Transfer Data Format
Transfer Clock⁽¹⁾
Transfer data: 8 bits long
See Tables 21.3 and 21.4
Transmit Start Condition
Set registers associated with the waveform generating function, the GiMR and GiERC
registers (i=0,1). Then, set as is written below after at least one transfer clock cycle.
• Set the TE bit in the GiCR register to "1" (transmit enabled)
• Set the TI bit in the GiCR register to "0" (data in the GiTB register)
Receive Start Condition
Set registers associated with the waveform generating function, the GiMR and GiERC
registers. Then, set as is written below after at least one transfer clock cycle.
• Set the RE bit in the GiCR register to "1" (receive enabled)
• Set the TE bit to "1" (transmit enabled)
• Set the TI bit to "0" (data in the GiTB register)
Interrupt Request
• While transmitting, one of the following conditions can be selected to set the SIOiTR
bit to "1" (interrupt requested) (See Figure 10.14):
_ _{The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and}
data is transferred to the transmit register from the GiTB register
_ _{The IRS bit is set to "1" (transmission completed) and data transfer from the}
transmit register is completed
• While receiving, the following condition can be selected to set SIOiRR bit is set to "1"
(data reception is completed):
Error Detection
Data is transferred from the receive register to the GiRB register (See Figure 10.14)
Overrun error⁽²⁾
This error occurs, when the next data reception is started and the 8th bit of the next
data is received before reading the GiRB register
Selectable Function
• LSB first or MSB first
Select either bit 0 or bit 7 to transmit or receive data
NOTES:
1. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive
shift operation enabled).
2. When an overrun error occurs, the GiRB register is indeterminate.
The ISTxDi pin outputs a high-level ("H") signal between selecting operating mode and starting transfer.
Table 21.3 Clock Settings (Communication Unit 0)
Transfer Clock
f8
f2n(1)
Input from ISCLK0
G0MR Register
CKDIR Bit
0
0
1
CCS Register
CCS0 Bit
CCS1 Bit
1
1
0
1
-
-
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Rev. 1.00 Nov. 01, 2005 ^{Page 256} of 330
REJ09B0271-0100