M32C80 Datasheet, PDF (136/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
12. DMAC
(1) When 8-bit data is transferred
or when 16-bit data is transferred with a 16-bit data bus from an even source address
CPU Clock
Address
Bus
CPU Use
Source
Destination
CPU Use
RD Signal
WR Signal
Data bus
CPU Use
Source
Destination
CPU Use
(2) When 16-bit data is transferred from an odd source address
or when 16-bit data is transferred and 8-bit bus is used to access a source address
CCPPUUCClolocckk
Address
Bus
CPU Use
RD Signal
WR Signal
Data Bus
CPU Use
Source Source + 1
Destination
Source Source + 1
Destination
CPU Use
CPU Use
(3) When one wait state is inserted into the source-read bus cycle under the conditions in (1)
CPU Clock
Address
Bus
RD Signal
WR Signal
Data Bus
CPU Use
CPU Use
Source
Destination
Source
Destination
CPU Use
CPU Use
(4) When one wait state is inserted into the source-read bus cycle under the conditions in (2)
CPU Clock
Address
Bus
RD Signal
CPU Use
Source
Source + 1
Destination
CPU Use
WR Signal
Data Bus
CPU Use
Source
Source + 1
Destination
CPU Use
NOTE:
1. The above applies when the destination-write bus cycle is 2 CPU clock cycles (=1 bus cycle).
However, if the destination-write bus cycle is pleaced under these conditions, it will change to
the same timing as the source-read cycle illustrated above.
Figure 12.6 Transfer Cycle Examples with the Source-Read Bus Cycle
Rev. 1.00 Nov. 01, 2005 Page 117 of 330
REJ09B0271-0100