M32C80 Datasheet, PDF (183/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
15. Three-Phase Motor Control Timer Functions
Timer Ai Mode Register (i=1, 2, 4)
b7 b6 b5 b4 b3 b2 b1 b0
0 100 1 0
Symbol
Address
After Reset
TA1MR, TA2MR, TA4MR 035716, 035816, 035A16 0016
Bit
Symbol
Bit Name
TMOD0 _{Operating Mode}
TMOD1 ^{Select Bit}
MR0 Reserved Bit
Function
RW
Set to "102" (one-shot timer
mode) when using the three-phase RW
motor control timer function
Set to "0"
RW
MR1
MR2
External Trigger Select
Bit
Trigger Select Bit
Set to "0" when using the three-phase
motor control timer function
RW
Set to "1" (selected by the TRGSR
register) when using the three-
RW
phase motor control timer function
MR3 Set to "0" with the three-phase motor control timer function
RW
b7 b6
TCK0
0 0: f1
RW
Count Source Select Bit 0 1: f8
1 0: f2n(1)
TCK1
1 1: fC32
RW
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Timer B2 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
00 00 0
Symbol
TB2MR
Address
035D16
After Reset
00XX 00002
Bit
Symbol
TMOD0
TMOD1
MR0
MR1
Bit Name
Function
RW
Operating Mode
Select Bit
Set to "002" (timer mode) when using
the three-phase motor control timer RW
function
Disabled when using the three-phase motor control timer function.
When write, set to "0".
When read, its content is indeterminate.
MR2 Set to "0" when using three-phase motor control timer function RW
MR3 ^{Nothing is assigned. When write, set to "0".}
When read, its content is indeterminate.
RW
b7 b6
TCK0
0 0: f1
RW
Count Source Select Bit 0 1: f8
1 0: f2n(1)
TCK1
1 1: fC32
RW
NOTE:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 15.7 TA1MR, TA2MR and TA4MR Registers, TB2MR Register
Rev. 1.00 Nov. 01, 2005 Page 164 of 330
REJ09B0271-0100