M32C80 Datasheet, PDF (78/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
8. Clock Generation Circuit
System Clock Control Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0 10000
Symbol
CM1
Address
000716
After Reset
0010 00002
Bit
Symbol
Bit Name
Function
RW
All Clock Stop Control 0: Clock oscillates
CM10 _{Bit(2, 5)}
1: All clocks stop (stop mode)⁽³⁾
RW
Reserved Bit
Set to "0"
RW
(b4 - b1)
Reserved Bit
(b5)
Set to "1"
RW
Reserved Bit
Set to "0"
RW
(b6)
CM17
CPU Clock Select
Bit 1^(4,5)
0: Main clock
1: PLL clock
RW
NOTES:
1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enabled).
2. When the CM10 bit is set to "1", the clock applied to XOUT becomes "H" and the built-in feedback
resistor is disabled. XIN, XCIN and XCOUT are placed in high-impedance states.
3. When the CM10 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002"
(divide-by-8 mode). When the CM20 bit is set to "1" (oscillation stop detect function enabled) or the
CM21 bit to "1" (on-chip oscillator selected), do not set the CM10 bit to "1".
4. The CM17 bit setting is enabled only when the CM21 bit in the CM2 register is set to "0". Use the
procedure shown in Figure 8.12 to set the CM17 bit to "1".
5. If the PM21 bit in the PM2 register is set to "1" (clock change disabled), the CM10 and CM17 bits do
not change when written.
If the PM22 bit in the PM2 register is set to "1" (on-chip oscillator clock as watchdog timer count
source), the CM10 bit setting does not change when written.
Figure 8.3 CM1 Register
Rev. 1.00 Nov. 01, 2005 Page 59 of 330
REJ09B0271-0100