M32C80 Datasheet, PDF (34/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
3. Memory
3. Memory
Figure 3.1 shows a memory map of the M32C/80 Group.
The M32C/80 Group provides 16-Mbyte address space addressed from 00000016 to FFFFFF16.
The fixed interrupt vectors are allocated from address FFFFDC16 to FFFFFF16. It stores the starting ad-
dress of each interrupt routine.
The internal RAM is allocated from address 00040016 to higher. For example, a 8-Kbyte internal RAM is
allocated from address 00040016 to 0023FF16. Besides storing data, it becomes stacks when the subrou-
tine is called or an interrupt is acknowledged.
SFRs, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O,
timers, is allocated from address 00000016 to 0003FF16. All blank spaces within SFRs are reserved and
cannot be accessed by users.
The special page vector table is addressed from FFFE0016 to FFFFDB16. It is used for the JMPS instruc-
tion and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
In microprocessor mode, some spaces are reserved and cannot be accessed by users.
00000016
00040016
0023FF16
01000016
SFRs
Internal RAM
Reserved Space
External Space
FFFE0016
Special Page
Vector Table
FFFFDC16
Undefined Instruction
Overflow
BRK Instruction
Address Match
Watchdog Timer⁽¹⁾
FFFFFF16
FFFFFF16
NMI
Reset
NOTE:
1. Watchdog timer interrupt and oscillation stop detection interrupt share vectors.
Figure 3.1 Memory Map
Rev. 1.00 Nov. 01, 2005 Page 15 of 330
REJ09B0271-0100