M32C80 Datasheet, PDF (193/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
16. Serial I/O
UARTi Special Mode Register 3 (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U0SMR3 to U4SMR3 036516, 02E516, 033516, 032516, 02F516 0016
Bit
Symbol
Bit Name
Function
RW
SSE
SS Pin Function
Enable Bit⁽¹⁾
0: Disables SS pin function
1: Enables SS pin function
RW
CKPH
Clock Phase
Set Bit
0: No clock delay
1: Clock delay
RW
0: Selects the TxDi and RxDi pins
DINC
Serial Input Port
Set Bit
(master mode)
1: Selects the STxDi and SRxDi pins
RW
(slave mode)
NODC
Clock Output
Select Bit
0: CMOS output
1: N-channel open drain output
RW
ERR
Fault Error Flag⁽²⁾
0: No error
1: Error
RW
b7 b6 b5
DL0
0 0 0: No delay
0 0 1: 1-to-2 cycles of BRG count source
RW
0 1 0: 2-to-3 cycles of BRG count source
DL1
SDAi Digital Delay _{0 1 1: 3-to-4 cycles of BRG count source}
Time Set Bit^{(3, 4)} 1 0 0: 4-to-5 cycles of BRG count source ^RW
1 0 1: 5-to-6 cycles of BRG count source
DL2
1 1 0: 6-to-7 cycles of BRG count source
1 1 1: 7-to-8 cycles of BRG count source ^RW
NOTES:
1. Set the SS pin after the CRD bit in the UiC0 register is set to "1" (CTS/RTS function disabled).
2. The ERR bit is set to "0" by program. It is unchanged if set to "1".
3. Digital delay is generated from a SDAi output by the DL2 to DL0 bits in I²C mode. Set these bits to
"0002" (no delay) except in the I²C mode.
4. When the external clock is selected, approximately 100ns delay is added.
Figure 16.7 U0SMR3 to U4SMR3 Registers
Rev. 1.00 Nov. 01, 2005 Page 174 of 330
REJ09B0271-0100