M32C80 Datasheet, PDF (129/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
12. DMAC
DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt
request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a
DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. There-
fore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In
addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged.
Table 12.1 DMAC Specifications
Item
Specification
Channels
4 channels (cycle-steal method)
Transfer Memory Space
• From a desired address in a 16-Mbyte space to a fixed address in a
16-Mbyte space
• From a fixed address in a 16-Mbyte space to a desired address in a
16-Mbyte space
Maximum Bytes Transferred 128 Kbytes (when a 16-bit data is transferred) or 64 Kbytes (with an 8-
DMA Request Source⁽¹⁾
bit data is transferred)
________
________
Falling edge or both edges of signals applied to the INT0 to INT3 pins
Timers A0 to A4 interrupt requests
Timers B0 to B5 interrupt requests
UART0 to UART4 transmit and receive interrupt requests
A/D0 conversion interrupt request
Intelligent I/O interrupt request
Software trigger
Channel Priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority)
Transfer Unit
8 bits, 16 bits
Destination Address
Forward/fixed (forward and fixed directions cannot be specified when
specifying source and destination addresses simultaneously)
Transfer Mode Single Transfer Transfer is completed when the DCTi register (i = 0 to 3) is set to "000016"
Repeat Transfer When the DCTi register is set to "000016", the value of the DRCi register
is reloaded into the DCTi register and the DMA transfer is continued
DMA Interrupt Request Generation Timing When the DCTi register changes "000116" to "000016"
DMA Startup Single Transfer DMA starts when a DMA request is generated after the DCTi register is
set to "000116" or more and the MDi1 and MD0 bits in the DMDj register
(j = 0,1) are set to "012" (single transfer)
Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is
set to "000116" or more and the MDi1 and MDi0 bits are set to "112"
(repeat transfer)
DMA Stop
Single Transfer DMA stops when the MDi1 and MDi0 bits are set to "002" (DMA dis-
abled) and the DCTi register is set to "000016" (0 DMA transfer) by DMA
transfer or write
Repeat Transfer DMA stops when the MDi1 and MDi0 bits are set to "002" and the DCTi
register is set to "000016" and the DRCi register set to "000016"
Reload Timing to the DCTi
When the DCTi register is set to "000016" from "000116" in repeat trans-
or DMAi Register
fer mode
DMA Transfer Cycles
Minimum 3 cycles between SFRs and internal RAM
NOTE:
1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.
Rev. 1.00 Nov. 01, 2005 Page 110 of 330
REJ09B0271-0100