M32C80 Datasheet, PDF (280/352 Pages) Renesas Technology Corp – 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/80 Group
21. Intelligent I/O (Communication Function)
Table 21.11 Register Settings in HDLC Processing Mode
Register
GiMR
GiEMR
GiCR
GiETC
GiERC
GiIRF
GiCMP0,
GiCMP1
GiCMP2
GiCMP3
GiMSK0,
GiMSK1
GiTCRC
GiRCRC
GiTO
GiRI
GiRB
GiTB
CCS
i=0, 1
Bit
Function
GMD1, GMD0 Set to "112"
CKDIR
Set to "0"
UFORM
Set to "0"
IRS
Select what causes the transmit interrupt to be generated
7 to 0
Set to "1111 01102"
TI
Transmit buffer empty flag
TXEPT
Transmit register empty flag
RI
Receive complete flag
TE
Transmit enable bit
RE
Receive enable bit
TCRCE
Select whether transmit CRC is used or not
TBSF1, TBSF0 Transmit bit stuffing
CMP2E to CMP0E Select whether received data is compared or not
CMP3E
Set to "1"
RCRCE
Select whether receive CRC is used or not
RSHTE
Set to "1" to use it in the receiver
RBSF1, RBSF0 Receive bit stuffing
BSERR
Set to "0"
IRF3 to IRF0
Select what causes an interrupt to be generated
7 to 0
Write "FE16" to abort processing
7 to 0
7 to 0
7 to 0
Data to be compared
Write "7E16"
Write "0116" to abort processing
15 to 0
15 to 0
7 to 0
7 to 0
7 to 0
7 to 0
CCS1, CCS0
CCS3, CCS2
Transmit CRC calculation result can be read
Receive CRC calculation result can be read
Data, which is output from a transmit data generation circuit, can be read
Set data input to a receive data generation circuit
Received data is stored
For transmission: write data to be transmitted
For reception: received data for comparison is stored
Select the HDLC processing clock
Select the HDLC processing clock
Rev. 1.00 Nov. 01, 2005 ^{Page 261} of 330
REJ09B0271-0100