SAB82538 Datasheet, PDF (93/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.6.3.3 Priority (HDLC/SDLC Mode Only)
To ensure that all competing stations are given a fair access to the transmission
medium, once a station has successfully completed the transmission of a frame, it is
given a lower level of priority. This priority mechanism is based on the requirement that
a station may attempt transmitting only when a determined number of consecutive 1’s
are detected on the bus.
Normally, a transmission can start when eight consecutive 1’s on the bus are detected
(through pin C×D). When an HDLC frame has been successfully transmitted, the internal
priority class is decreased. Thus, in order for the same station to be able to transmit
another frame, ten consecutive 1’s on the bus must be detected. This guarantees that
the transmission requests of other stations are satisfied before a same station is allowed
a second bus access. When ten consecutive 1’s have been detected, transmission is
allowed again and the priority class is increased (to “eight 1’s”).
Inside a priority class, the order of transmission (individual priority) is based on the HDLC
address, as explained in the preceding paragraph. Thus, when a collision occurs, it is
always the station transmitting the only zero (i.e. all other stations transmit a one) in a bit
position of the address field that wins, all other stations cease transmission immediately.
2.6.3.4 Timing Modes
If a bus configuration has been selected, the ESCC8 provides two timing modes,
differing in the time interval between sending data and evaluation of the transmitted data
for collision detection.
q Timing mode 1 (CCR0: SC1, SC0 = 01)
Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated
1/2 at the CxD pin clock period later with the falling clock edge.
q Timing mode 2 (CCR0: SC1, SC0 = 11)
Data is output with the falling clock edge and evaluated with the next falling clock
edge. Thus one complete clock period is available between the instant when data is
output and collision detection.
Semiconductor Group
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