SAB82538 Datasheet, PDF (241/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Clock Timing
Parameter
RxCLK clock period (Note 1)
(Note 3)
RxCLK high time (Note 1)
(Note 3)
RxCLK low time
(Note 1)
(Note 3)
TxCLK clock period
TxCLK high time
TxCLK low time
XTAL1 clock period (Note 2)
(Note 3)
XTAL1 high time (Note 2)
(Note 3)
XTAL1 low time
(Note 2)
(Note 3)
No. Symbol
58 t_c(RxC)
t 59
w(RxCH)
t 60
w(RxCL)
61 t_c(TxC)
t 62
w(TxCH)
t 63
w(TxCL)
64
t_c(XTAL1)
65
t_w(XTAL1H)
66
t_w(XTAL1L)
Limit Values
Unit
H
H-10
min. max. min. max.
480
100
ns
50
50
ns
150
45
ns
22
22
ns
150
45
ns
22
22
ns
480
100
ns
150
45
ns
150
45
ns
480
100
ns
75
75
ns
150
45
ns
35
35
ns
150
45
ns
35
35
ns
Note 1: Externally clocked: clock mode 0, 1 except ASYNC, BCR = 16.
Note 2: Externally clocked: clock mode 4 except ASYNC, BCR = 16;
Master clock mode generally.
Note 3: Internally clocked: HDLC, BISYNC: DPLL + baud rate generator used.
ASYNC all other clocking modes.
Semiconductor Group
241