SAB82538 Datasheet, PDF (142/253 Pages) Infineon Technologies AG – ICs for Communications

Interrupt Port Configuration (READ/WRITE)
Value after RESET: 00_H
7
IPC VIS ROTM SLA2 SLA1 SLA0 CASM IC1
SAB 82538
SAF 82538
HDLC Mode
0
IC0 (039/079/0B9/0F9)
(139/179/1B9/1F9)
Note: Unused bits have to be set to logical “0”.
IPC is accessible via eight channel addresses (039_H to 1F9_H).
VIS…
Masked Interrupts Visible (version 2 upward)
0… Masked interrupt status bits are not visible.
1… Masked interrupt status bits are visible.
ROTM…
Rotating Interrupt Priority Mode (version 2 upward)
Together with bit IVA.ROT the interrupt priority mode is selected.
0… With IVA.ROT = 1 the priorities of all 8 serial channels are rotated
cyclically after an interrupt has been serviced. The channel last
serviced is assigned the lowest priority of all (refer to
chapter 2.2.3.1.).
1… With IVA.ROT = 0 the priority adjustment is performed only on 7
channels while one channel is fixed to highest priority level (refer to
chapter 2.2.3.1).
SLA2 – SLA0… Slave Address
Only used in Slave Cascading Mode (refer to CASM).
CASM…
Cascading Mode
0… Slave Cascading Mode
Pins IE0, IE1 and IE2 are used as inputs. Interrupt acknowledge is
accepted if an interrupt signal has been generated and the values on
pins IE0, IE1 and IE2 correspond to the programmed values in SLA0,
SLA1 and SLA2 (slave address).
1… Daisy Chaining Mode
Pin IE0 as Interrupt Enable Output and pin IE1 as Interrupt Enable
Input are used for building a Daisy Chain. Pin IE2 is not used. Interrupt
acknowledge is accepted if an interrupt signal has been generated and
Interrupt Enable Input IE1 is active “high” during a subsequent INTA
cycle(s). If pin INT goes active, Interrupt Enable Output IE0 is
immediately set “low”.
Semiconductor Group
142