SAB82538 Datasheet, PDF (193/253 Pages) Infineon Technologies AG – ICs for Communications

RFRD…
STI…
XF…
HUNT...
XME...
XRES…
SAB 82538
SAF 82538
BISYNC Mode
Receive FIFO Read Enable
The CPU can have access to RFIFO by issuing the RFRD command before
threshold level or the end condition (TCD) are fulfilled. After issuing the
RFRD command, the CPU has to wait for TCD interrupt, before reading
RBC and RFIFO. The number of valid bytes is determined by reading the
RBCL register.
Start Timer
The internal timer is started.
Note: The timer is stopped by rewriting the TIMR register after start.
Transmit Frame
q Interrupt Mode
After having written up to 32 bytes/16 words to the XFIFO, this command
initiates the transmission of data.
q DMA Mode
After having written the amount of data to be transmitted to the XBCH,
XBCL registers, this command initiates the data transfer from system
memory to ESCC8 by DMA. Serial data transmission starts as soon as
32 bytes/16 words are stored in the XFIFO or the Transmit Byte Counter
value is reached.
Enter Hunt Phase
This command forces the receiver to immediately go into the Hunt state.
Synchronization is lost and the receiver starts searching for SYN
characters.
Transmit Message End (used in interrupt mode only!)
Indicates that the data block written last to the transmit FIFO completes the
current frame. The ESCC8 can terminate the transmission operation
properly by appending the CRC sequence to the data. After that, IDLE is
transmitted.
In DMA Mode, the end of the frame is determined by the Transmit Byte
Count in XBCH, XBCL, thus, XME is not used in this case.
Transmitter Reset
XFIFO is cleared of any data and IDLE (logical “1s”) is transmitted. This
command can be used by the CPU to abort current data transmission. In
response to XRES an XPR interrupt is generated.
Semiconductor Group
193