SAB82538 Datasheet, PDF (139/253 Pages) Infineon Technologies AG – ICs for Communications

Address Mask Low (WRITE)
(Version 2 upwards)
Value after RESET: 00_H
7
AML
AML7
SAB 82538
SAF 82538
HDLC Mode
0
AML0 (offset: 36)
The Receive Address Low Byte (RAL1) can be masked by setting corresponding bits in
this mask register to allow extended broadcast address recognition. This feature is
applicable in all operating modes with address recognition. The function is disabled if all
bits of this register are set to zero (RESET value).
Address Mask High (WRITE)
(Version 2 upwards)
Value after RESET: 00_H
7
AMH
AMH7
0
AMH0 (offset: 37)
The function is similar to AML but with respect to register RAH1.
Global Interrupt Status Register (READ)
Value after RESET: 00_H
7
GIS PIA PIB PIC PID CII
0
CN2 CN1 CN0 (038/078/0B8/0F8)
(138/178/1B8/1F8)
This status register points to pending
– channel assigned interrupts (ISR0_x, ISR1_x)
– universal port interrupts (PISA..D).
GIS is accessible via eight channel addresses (038_H to 1F8_H).
PIA, PID… Port Interrupt Indication
These status bits point to pending interrupts in corresponding Port Interrupt
Status registers PISA…PISD. They may be set independently from channel
assigned interrupts.
Semiconductor Group
139