SAB82538 Datasheet, PDF (74/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Oversampling (3 samples) around the nominal bit center in conjunction with majority
decision is provided for every received bit (including Start Bit).
The synchronization lasts for one character, the next incoming character causes a new
synchronization to be performed. As a result, the demand for high clock accuracy is
reduced. Two communication stations using the asynchronous procedure are clocked
independently, their clocks need not be in phase or locked to exactly the same frequency
but, in fact, may differ from one another within a certain range.
Isochronous Mode
Prerequisites:
q Bit clock rate 1 selected (CCR1.BCR = 0)
q Clock mode 2, 3a, 6, or 7a (DPLL mode) has to be used in conjunction with FM0, FM1
or Manchester encoding.
The isochronous mode uses the asynchronous character format. However, each data bit
is only sampled once (no oversampling).
In clock modes 0 and 1, the input clock has to be externally phase locked to the data
stream. This mode allows much higher transfer rates. Clock modes 3b, 4 and 7b are not
recommended due to difficulties with bit synchronization when using the internal baud
rate generator.
In clock modes 2, 3a, 6, and 7a, clock recovery is provided by the internal DPLL. Correct
synchronization of the DPLL is achieved if there are enough edges within the data
stream, which is generally ensured only if Bi-Phase encoding (FM0, FM1 or Manchester)
is used.
2.4.2.2 Storage of Data
If the receiver is enabled, received data is stored in RFIFO (the LSB is received first).
Moreover, the CD input may be used to control data reception. Character length, the
number of Stop Bits and the optional parity bit are checked. Storage of parity bits can be
disabled. Errors are indicated via interrupts. Additionally, the character error status
(framing and parity) can optionally be stored in the RFIFO (refer to chapter 4.2.2).
Filling of the accessible part of RFIFO is controlled by
q A programmable threshold level
q Detection of the programmable Termination Character (optional).
Additionally, the Time-Out condition as optional status information indicates that a
certain time (refer to register ISR0) has elapsed since the reception of the last character.
Semiconductor Group
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