SAB82538 Datasheet, PDF (191/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
BISYNC Mode
Interrupt Mode
Selected if DMA bit in XBCH is reset.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following an XPR
interrupt.
DMA Mode
Selected if DMA bit in XBCH is set.
Prior to any data transfer, the actual byte count to be transmitted must be written to the
XBCH, XBCL registers by the user. Correct transmission of data in the case of word
access and of an odd number of bytes specified in XBCH, XBCL is guaranteed.
If data transfer is then initiated via the CMDR register (command XF), the ESCC8
autonomously requests the correct amount of block data transfers (n×BW + REST;
BW = 32, 16; n = 0, 1,…).
Note: Addresses within the 32-byte address space of the FIFO all point to the same
byte/word, i.e. current data can be accessed with any address within the valid
range.
Status Register (READ)
7
0
STAR XDOV XFW RFNE SYNC 0 CEC CTS 0 (offset: 20)
XDOV…
XFW…
RFNE…
SYNC...
Transmit Data Overflow
More than 32 bytes have been written to the XFIFO.
This bit is reset by:
– a transmitter reset command XRES
– or when all bytes in the accessible half of the XFIFO have been moved
into the inacessible half.
Transmit FIFO Write Enable
Data can be written to the XFIFO.
RFIFO Not Empty
This bit is set if the accessible part of RFIFO holds at least one valid byte.
Synchronization Status
The bit is reset after the HUNT command has been issued. It indicates that
the receiver has lost synchronization and is searching for the presence of
a SYN character. If found, SYNC will be immediately set, the SCD interrupt
is generated (if enabled), and filling the RFIFO with received data is started.
Semiconductor Group
191