SAB82538 Datasheet, PDF (82/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.6 Serial Interface (Layer-1 functions)
The eight serial interfaces of the ESCC8 provide eight fully independent communication
channels, supporting layer-1 functions to a high degree by various means of clock
generation and clock recovery.
Note: Since the eight serial channels are completely independent, the functions
described in this document apply to all eight channels. For simplification purposes
the indices 0 to 7 will usually be omitted from the signal names, and are implied.
2.6.1 Clock Modes
The ESCC8 includes an internal Oscillator (OSC) as well as independent Baud Rate
Generator (BRG) and Digital Phase Locked Loop (DPLL) circuitry for each serial
channel.
The transmit and receive clock can be generated either
– externally, and supplied via the R×CLK and/or T×CLK pins, or
– internally, by means of the
q OSC and/or BRG, and
q DPLL, recovering the receive (+ optionally transmit) clock from the received data
stream.
There are a total of 8 different clocking modes programmable via the CCR1 register,
providing a wide variety of clock generation and clock pin functions, as shown in table 4.
Table 4
Overview of Clock Modes
Type
Receive Clock
Source
RxCLK Pins
Clock
Generation
Externally
Mode
0, 1, 5
Transmit Clock
DPLL
OSC
BRG
TxCLK Pins
RxCLK Pins
Internally
Externally
2, 3a, 6, 7a
4
3b, 7b
0a, 2a, 6a
1, 5
DPLL
BRG ./. 16
OSC
BRG
Internally
3a, 7a
2b, 6b
4
0b, 3b, 7b
Semiconductor Group
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