SAB82538 Datasheet, PDF (177/253 Pages) Infineon Technologies AG – ICs for Communications

Interrupt Vector Address (WRITE)
Value after RESET: 00_H
7
IVA
T7 T6 T5 T4 T3
SAB 82538
SAF 82538
ASYNC Mode
0
T2 ROT EDA (038/078/0B8/0F8)
(138/178/1B8/1F8)
Note: Unused bits have to be set to logical “0”.
IVA is accessible via eight channel addresses (38_H to 1F8_H).
Version 2 upward provides dynamic adjustment of channel priorities by programming the
“highest priority channel”. Selection of the “highest priority channel” is done with every
write access to IVA in conjunction with the channel assigned IVA register address:
IVA Register Address: Highest Priority Channel
38_H
0
78_H
1
B8_H
2
F8_H
3
138_H
4
178_H
5
1B8_H
6
1F8_H
7
The priority level becomes valid with the end of the write access to the IVA register (rising
edge of WR or DS, whichever applies) and remains stable until a new write access to
this register occurs.
T7– T6… Device Address
These bits define the value of bits 6 and 7 of the interrupt vector which is
sent out on the data bus (D0…D7) during the interrupt acknowledge cycle.
T5…
Device Address
Version 1: Device Address
This bit defines the value of bit 5 of the interrupt vector which is sent out
on the data bus (D0…D7) during the interrupt acknowledge cycle.
Version 2: Device Address Extension
In Interrupt vector mode 2 (bit EDA set) this bit defines the value of bit 5
of the interrupt vector which is sent out on the data bus (D0…D7) during
the interrupt acknowledge cycle.
Semiconductor Group
177