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SAB82538 Datasheet, PDF (246/253 Pages) Infineon Technologies AG – ICs for Communications
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SAB 82538
SAF 82538
Transmit Cycle Timing
Parameter
No. Symbol
Transmit data rate
ext. clocked (except
ASYNC, BCR = 16)
int. clocked (HDLC,
BISYNC: only DPLL)
int. clocked
(all other internal modes)
Clock period
ext. clocked (except
ASYNC, BCR = 16)
73 tc(XC)
int. clocked (HDLC,
BISYNC: only DPLL)
int. clocked
(all other internal modes)
Transmit data delay
Transmit data delay
74 tp(TxD)
74C
RxD to TxD delay
t 74A p(RxD-TxD)
(SDLC loop, “Off Loop” state)
Clock output to transmit data delay 75
Collision data and CTS setup time 76
Collision data and CTS hold time 77
Request send delay
78
normal operation
bus configuration
tp(XC-TxD)
tsu(CxD)
th(CxD)
tp(RTS)
CTS status change to INT delay
tCTS-INT
Limit Values
Unit
H
H-10
min. max. min. max.
2
10 Mbit/s
2
2
Mbit/s
2
2
Mbit/s
480
100
ns
480
480
ns
480
480
ns
70
70 ns
75
75 ns
50
50 ns
– 30 20
10
30
– 30 20 ns
10
ns
30
ns
65
65 ns
50
50 ns
T73
T73 ns
+ 60
+ 60
Semiconductor Group
246
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