SAB82538 Datasheet, PDF (18/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Pin Definitions and Function (cont’d)
Pin No. Symbol
73
DACK0
74
DACK1
75
DACK2
76
DACK3
77
DACK4
78
DACK5
79
DACK6
80
DACK7
14
RXD0
16
RXD1
20
RXD2
22
RXD3
112
RXD4
110
RXD5
108
RXD6
106
RXD7
49
RXCLK0
50
RXCLK1
51
RXCLK2
52
RXCLK3
69
RXCLK4
70
RXCLK5
71
RXCLK6
72
RXCLK7
Input (I)
Function
Output (O)
I
I
(O/oD)
DMA Acknowledge (Channel 0 … 7)
A low signal on these pins informs the ESCC8
that the requested DMA cycle controlled via DRT
or DRR of the corresponding channel is in
progress, i.e. the DMA controller has achieved
bus mastership from the CPU and will start data
transfer cycles (either write or read).
In conjunction with a read or write operation these
inputs serve as Access Enable (similar to CS) to
the respective FIFOs. If DACK is active, the input
to pins A1…A8 is ignored and the FIFOs are
implicitly selected. A0 and BHE/BLE are used to
select byte or word access.
If not used, these pins must be connected to V_DD.
Receive Data (Channel 0 … 7)
Serial data is received on these pins.
May be switched to T×D function via bit
CCR2.SOC1.
I
Receive Clock (Channel 0 … 7)
The function of these pins depends on the
selected clock mode.
In each channel, R×CLKn may supply either
– the receive clock (clock mode 0), or
– the receive and transmit clock
(clock mode 1, 5), or
– the clock input for the baud rate generator
(clock mode 2, 3).
Semiconductor Group
18