SAB82538 Datasheet, PDF (25/253 Pages) Infineon Technologies AG – ICs for Communications

1.4 System Integration
1.4.1 General Aspects
SAB 82538
SAF 82538
Figure 3
General System Integration of ESCC8
Figure 3 gives a general overview of system integration of ESCC8.
The ESCC8’s bus interface consists of an 8/16-bit bidirectional Data bus (D0-D15), nine
Address Line inputs (A0-A8), three control inputs (RD / DS, WR / R/W, CS), five signals
for interrupt support (INT, INTA, IE0-2) and a 16-channel DMA interface. Mode input pins
(strapping options) allow the bus interface to be configured for 8/16-bit bus width and for
either Siemens/Intel or Motorola environment.
Generally, there are two types of transfers occurring via the system bus:
– Command/Status transfers, which are always controlled by the CPU. The CPU sets
the operation mode (Initialization), controls function sequences and gets status
information by writing or reading the ESCC8’s registers (via CS, WR or RD, and
register address via A0-A8, BHE).
– Data Transfers, which are effectively performed by DMA without CPU interaction using
the ESCC8’s DMA interface (DMA Mode). Optionally, interrupt controlled data transfer
can be done by the CPU (Interrupt Mode).
Semiconductor Group
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