SAB82538 Datasheet, PDF (107/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
The activities at both serial and CPU interface during frame transmission (supposed
frame length = 70 bytes) are shown in figure 45.
Figure 45
Interrupt Driven Transmission Sequence Example (HDLC)
3.3.1.2 DMA Mode
Prior to data transmission, the length of the next frame (or the next block of characters)
to be transmitted must be programmed via the Transmit Byte Count Registers (XBCH,
XBCL). The resulting byte count equals the programmed value plus one byte, i.e. since
12 bits are provided via XBCH, XBCL (XBC11…XBC0) a frame length of 1 up to 4096
bytes (4 Kbytes) can be selected.
After this, data transmission can be initiated by command (XTF or XIF in HDLC/SDLC
mode, XF in ASYNC and BISYNC mode). The ESCC8 will then autonomously request
the correct amount of write cycles by activating the DRT line for as long as necessary,
taking into account the selected data bus width (i.e. byte or word accesses). For a frame
length of L = (n × 32 + remainder) bytes (n = 0, 1,…,128), block data transfers of
32 bytes/16 words or remainder (÷2) bytes (words) are requested whenever a 32-byte
FIFO half (transmit pool) is empty and accessible to the DMA controller.
The following figure gives an example of a DMA driven transmission sequence with a
supposed frame length of 70 bytes, i.e. programmed transmit byte count (XCNT) equal
to 69 bytes.
Semiconductor Group
107