SAB82538 Datasheet, PDF (204/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
BISYNC Mode
Channel Configuration Register 2 (READ/WRITE)
Value after RESET: 00_H
The meaning of the individual bits in CCR2 depends on the clock mode selected via
CCR1 as follows:
7
0
CCR2 clock mode 0a, 1
SOC1 SOC0 0
0
0 RWX 0 DIV (offset: 2E)
clock mode 0b, 2, 3, 6, 7
BR9 BR8 BDF SSEL TOE RWX 0 DIV
clock mode 4
SOC1 SOC0 0
0 TOE RWX 0 DIV
clock mode 5
SOC1 SOC0 XCS0 RCS0 TOE RWX 0 DIV
Note: Unused bits have to be set to logical “0”.
SOC1, SOC0… Special Output Control
In a bus configuration (selected via CCR0) defines the function of pin RTS
as follows:
0X… RTS output is activated during transmission of characters.
10… RTS output is always high (RTS disabled).
11… RTS indicates the reception of a data frame (active low).
In a point-to-point configuration (selected via CCR0) the T×D and R×D pins
may be flipped
0X… data is transmitted on T×D, received on R×D (normal case).
1X… data is transmitted on R×D, received on T×D.
BR9, BR8… Baud Rate, Bit 9-8
High order bits, see description of BGR register.
XCS0, RCS0... Transmit/Receive Clock Shift, Bit 0
Together with XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR), determines
the clock shift relative to the frame synchronization signal of the Transmit
(Receive) time-slot.
A clock shift of 0 ... 7 bits is programmable (clock mode 5 only).
Semiconductor Group
204