SAB82538 Datasheet, PDF (45/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.2.3.2 Interrupt Polling
After ESCC8 has requested an interrupt by activating its INT pin, the CPU must first read
the Global Interrupt Status register GIS to identify parallel port and/or channel related
interrupt indications:
q Channel related interrupts are indicated via bit GIS.CII (Channel Interrupt Indication)
and the number of the requesting channel (GIS.CN2..0). After reading the assigned
interrupt status registers ISR0_x and ISR1_x, the pointer in register GIS is cleared or
updated if another channel requires interrupt service.
q The 28-bit universal port is divided into four groups (port A,B,C: 8 lines each, port D:
4 lines) which all have the same lowest interrupt priority. Pending interrupts are
pointed out directly via GIS.PIA..D. Reading the assigned interrupt status registers
(PISA..D) will reset the corresponding indication in GIS.
If all pending interrupts are acknowledged (GIS is reset), pin INT goes inactive.
2.2.3.3 Vectored Interrupt Structure
After ESCC8 has requested an interrupt by activating its INT pin, the system (CPU or
peripherals) starts the interrupt acknowledge cycle by activating the INTA signal. If the
Intel bus interface mode is selected, the two-pulse’86 mode is supported. In Motorola
interface mode single pulse acknowledgement is implemented.
Interrupt acknowledge operation is determined by the selected interrupt cascading mode
(IPC register) in conjunction with the Interrupt Enable Signals IE0, IE1 and IE2:
q Slave Mode
The address of the slave under service has to be provided via inputs IE0, IE1 and IE2
during the valid INTA cycle. Interrupt acknowledge is accepted if this address
corresponds to the programmed value (IPC register).
If the ESCC8 is used in single device applications (no other device is present for
interrupt cascading), IE0..2 have to be fixed to a defined level corresponding to the
internally programmed address.
q Daisy Chaining Mode
IE0 as Interrupt Enable Output and IE1 as Interrupt Enable Input are used to build a
Daisy Chain (refer to chapter 1.4). Input IE2 is not used and has to be tied to VSS.
Interrupt acknowledge is accepted if IE1 is active during the valid INTA cycle. Output
IE0 follows the IE1 input. Additionally, IE0 is reset when INT goes active.
Activation of pin INT is prohibited
– during INTA cycles
– between the first and the second INTA cycle if Siemens/Intel mode is selected.
If interrupt acknowledge is accepted in one of the above modes, the ESCC8 generates
an interrupt vector which is output on D0-D7 of the data bus independent of the selected
bus interface mode (refer to figure 15).
Semiconductor Group
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