SAB82538 Datasheet, PDF (214/253 Pages) Infineon Technologies AG – ICs for Communications

PLLA…
CDSC…
RFO…
RPF…
SAB 82538
SAF 82538
BISYNC Mode
DPLL Asynchronous
This bit is only valid when the receive clock is supplied by the DPLL and
FM0, FM1 or Manchester data encoding is selected.
It is set when the DPLL has lost synchronization. Reception is disabled
(IDLE is inserted) until synchronization has been regained. Additionally,
transmission is also interrupted if the transmit clock is derived from the
DPLL.
Carrier Detect Status Change
Indicates that a state transition has occurred on CD. The actual state of CD
can be read from the VSTR register.
Receive FIFO Overflow
This interrupt is generated if RFIFO is full and a further character is
received. This interrupt can be used for statistical purposes and indicates
that the CPU does not respond quickly enough to an RPF or TCD interrupt.
Receive Pool Full
This bit is set if RFIFO is filled with data (character and optional status
information) up to the programmed threshold level.
Note: This interrupt is only generated in Interrupt Mode.
Interrupt Status Register 1 (READ)
Value after RESET: 00_H
7
0
ISR1
0
0 ALLS XDU TIN CSC XMR XPR (offset: 3B)
All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding
interrupt vector is output.
Note: If bit IPC.VIS is set to “1”, interrupt statuses in ISR1 may be flagged although they
are masked via register IMR1. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are visible in register GIS.
ALLS...
All Sent
This bit is set when the XFIFO is empty and the last character is completely
sent out on T×D.
Semiconductor Group
214