SAB82538 Datasheet, PDF (114/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
q DMA Controlled Data Transfer (DMA Mode)
Selected if DMA bit in XBCH is set.
If the RFIFO is filled up to its threshold level, the ESCC8 autonomously requests a
block data transfer by DMA by activating the DRRn line until all read cycles are
performed (the DRRn line remains active up to the beginning of the last read cycle).
This forces the DMA controller to continuously perform bus cycles till all bytes/words
are transferred from the ESCC8 to the system memory (level triggered transfer mode
of DMA controller).
If the RFIFO contains less bytes/words than defined via threshold level (one short
frame or the last part of a long frame) the ESCC8 requests a block data transfer of
size equal to the amount of data to be transferred.
Additionally, an RME interrupt is generated after the last byte has been transferred.
Further receiver DMA requests are blocked until an RMC command is issued in
response to RME.
The valid byte count of the whole frame can be determined by reading the RBCH, RBCL
registers following the RME interrupt.
Note: Addresses within the address space of the FIFO point all to the current data word/
byte, i.e. the current data byte can be accessed with any address within the 32-
byte range.
Transmit FIFO (WRITE) XFIFO (offset: 00… 1F)
Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) access depending
on the selected bus interface mode. The LSB is transmitted first.
q Interrupt Mode
Selected if DMA bit in XBCH is set to zero.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following an XPR
(or ALLS) interrupt.
q DMA Mode
Selected if DMA bit in XBCH is set to one.
Prior to any data transfer, the actual byte count of the frame to be transmitted must
be written to the XBCH, XBCL registers by the user.
If data transfer is then initiated via the CMDR register (command XTF or XIF), the
ESCC8 autonomously requests the correct amount of block data transfers
(n*BW + Remainder; BW = 32 or 16; n = 0, 1,… ).
Note: Addresses within the address space of the FIFO's all point to the current data
word/byte, i.e. the current data byte can be accessed with any address within the
32-byte range.
Semiconductor Group
114