SAB82538 Datasheet, PDF (120/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Mode Register (READ/WRITE)
Value after RESET: 00_H
7
HDLC Mode
0
MODE MDS1 MDS0 ADM TMD RAC RTS TRS TLP (offset: 22)
MDS1…
ADM…
MDS0… Mode Select
The operating mode of the HDLC controller is selected.
00… auto-mode
01… non auto-mode
10… transparent mode
11…extended transparent mode
Address Mode
The meaning of this bit varies depending on the selected operating mode:
• auto-mode, non auto-mode
Defines the length of the HDLC address field.
0… 8-bit address field
1… 16-bit address field
In transparent modes, this bit differentiates between two sub-modes:
• transparent mode
0… transparent mode 0; no address recognition.
1… transparent mode 1; high byte address recognition.
• extended transparent mode; without HDLC framing.
0… extended transparent mode 0
1… extended transparent mode 1
Note: In extended transparent modes, the RAC bit must be reset to enable
fully transparent reception.
Semiconductor Group
120