SAB82538 Datasheet, PDF (166/253 Pages) Infineon Technologies AG – ICs for Communications

Transmit Byte Count Low (WRITE)
7
XBCL XBC7
SAB 82538
SAF 82538
ASYNC Mode
0
XBC0 (offset: 2A)
Together with XBCH (bits XBC11…XBC8) this register is used in DMA Mode only, to
program the length (1…4096 bytes) of the next data block to be transmitted.
In terms of the value xbc, programmed in XBC11…XBC0 (xbc = 0…4095), the length of
the block in number of bytes is:
length = xbc + 1.
This allows the ESCC8 to request the correct amount of DMA cycles after an XF
command in CMDR.
Received Byte Count High (READ)
Value after RESET: 000xxxxx
7
RBCH DMA 0 CAS 0
see XBCH
RBC11
0
RBC8 (offset: 2B)
DMA, CAS… These bits represent the read-back value programmed in XBCH
RBC11– RBC8… Receive Byte Count (most significant bits)
No function in ASYNC mode.
Transmit Byte Count High (WRITE)
Value after RESET: 000xxxxx
7
XBCH DMA 0 CAS XC XBC11
0
XBC8 (offset: 2B)
Note: Unused bits have to be set to logical “0”.
DMA…
DMA Mode
Selects the data transfer mode of ESCC8 to/from System Memory.
0… Interrupt controlled data transfer (Interrupt Mode).
1… DMA controlled data transfer (DMA Mode).
Semiconductor Group
166