SAB82538 Datasheet, PDF (83/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
The transmit clock pins (TxCLK) may also output clock signals in certain clock modes if
enabled via CCR2.TOE.
The clocking source for the DPLL’s is always the internal BRG; the scaling factor
(divider) of the BRG can be programmed through CCR2 and BGR registers between 1,
2, 4, 6…2048.
The ESCC8’s system clock is always derived from the transmit clock or from the master
clock (if master clock mode is enabled).
Master Clock Capabilities
A new clock source can be defined as master clock to allow full functionality of the
microprocessor interface (access to all status and control registers and FIFOs, DMA and
interrupt support) independent from the receive and transmit clocks. This new function
(enabled via bit CCR0.MCE) is useful for modem applications where continuous
generation of the receive and especially of the transmit clock cannot be guaranteed. The
master clock has to be supplied via pin XTAL1 (or a crystal connected to XTAL1-2).
Depending on the version, the maximum clock rate is 10 MHz (SAB 82538H-10) or 2
MHz (SAB 82538H).
Notes:
q The master clock is applicable to all clock modes except clock mode 5. For details
refer to table 5.
q If bus configuration is selected in HDLC/SDLC mode (CCR0.SC2 .. 0), the One-
Insertion (CCR1.OIN) cannot be used in conjunction with the Master Clock feature.
q In SDLC Loop mode the Master clock option is not available.
q The conditions for the ratio between transmit clock, master clock and receive clock
frequencies must be fulfilled to guarantee correct function
(refer to the notes of table 5).
q The internal timers run with the master clock.
q The serial interface (transmitter and receiver) are not sequenced by the master clock
however the FIFOs, DMA-UNIT and TIMER are.
Clock Mode 0 (External Clocks)
Separate, externally generated receive and transmit clocks are supplied to the ESCC8
via their respective pins. The transmit clock can be directly supplied by pin TxCLK
(mode 0a) or generated by the internal baud rate generator from the clock supplied by
pin XTAL1 (mode 0b). In the latter case, the transmit clock can be output via pin TxCLK.
Semiconductor Group
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