SAB82538 Datasheet, PDF (46/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Implementation of the interrupt service routines should consider the two selectable
interrupt vector modes (bit IVA.EDA):
q Interrupt vector mode 1 (EDA = 0)
Interrupt vector includes: device address, version 2: parallel port indication, channel
identification, interrupt group
(+): fastest interrupt source identification (especially for interrupt groups 0..2).
(–): interrupt vector table needs 32 (version 2: 64) entry points, placement of this entry
field only in steps of 128 bytes (version 1: 3-bit device address; version 2: 2-bit
device address), fastest service requires implementation of up to 32 (64) interrupt
service routines.
In case more than one source is active, the generated vector refers to the interrupt
group with highest priority, and within a group to the requesting channel with highest
priority. Although universal port interrupts and their indications via register GIS are
independent from channel assigned interrupts, a vector with group 3, channel 7
indication may additionally refer to pending universal port interrupts. In version 2
upward the “PI”-bit of the interrupt vector indicates a pending parallel port interrupt.
Interrupt groups 0 to 2 are assigned to definite single interrupt indications per channel.
These are urgent receive and transmit interrupts which need to be serviced quickly.
Due to this, no read access to interrupt status registers is necessary: the
corresponding interrupt indication is reset after the INTA cycle has been finished.
Interrupt group 3 combines all other interrupt sources. Thus, the interrupt status
registers ISR0_x and ISR1_x which correspond to the requesting channel have to be
examined. Version 1: if channel 7 is indicated, the global status register GIS has to be
evaluated for pending channel and/or universal port interrupts. Version 2 upward: the
“PI”-bit indicates a pending parallel port interrupt separately from channel 7 interrupts.
The INT signal is reset when all interrupt indications are cleared (acknowledged). See
also exceptions in Daisy Chaining mode.
q Interrupt vector mode 2 (EDA = 1)
Interrupt vector includes: extended device address, interrupt group
(+): interrupt vector table needs only 4 entry points, placement of this entry field in
steps of 16 bytes (6-bit device address), only 4 different interrupt service routines
necessary.
(–): context switching for each channel necessary (via register GIS).
In case more than one source is active, the generated vector refers to the interrupt
group with highest priority. For identification of the requesting channel, register GIS
has to be read. Bits CN2..CN0 (channel number) have to be used for context
switching, i.e. for computing the pointer to channel assigned data structures.
Note: Universal port interrupts indications in register GIS are independent of
channel assigned interrupts. Thus, one of indications PIA..D may be set
although the generated interrupt vector refers to a group with priority and/or the
channel number is less than 7.
Semiconductor Group
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