SAB82538 Datasheet, PDF (110/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Figure 47
Interrupt Driven Reception Sequence Example (HDLC)
3.3.2.2 DMA Mode
If the RFIFO contains 32 bytes, the ESCC8 autonomously requests a block data transfer
by DMA by activating the DRR line for as long as the start of the 32nd (byte access) or
16th (word access) read cycle. This forces the DMA controller to continuously perform
bus cycles till 32 bytes are transferred from the ESCC8 to the system memory. If the
RFIFO contains less than 32 bytes, the ESCC8 requests the correct amount of transfer
cycles depending on the contents of the RFIFO and taking into account the selected bus
width.
Note: All available status information for each frame/data block after the end conditions
(RME or TCD) and for each character is the same as described above.
After the DMA controller has been set up for the reception of the next frame, the CPU
must issue a RMC command to acknowledge the completion of received data
processing. The ESCC8 will not initiate further DMA cycles by activating the DRR line
prior to the reception of RMC.
In HDLC/SDLC mode the RECEIVE STATUS REGISTER is automatically read from the
RFIFO with the last DMA-READ cycle of the received frame.
The status information after a RME interrupt is the same as in the interrupt driven mode.
The following figure gives an example of a DMA controlled reception sequence,
supposing that a “long” frame (66 bytes) followed by two short frames (6 bytes each) is
received.
Semiconductor Group
110