SAB82538 Datasheet, PDF (69/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.3.4.4 Extended Transparent Transmission and Reception
When programmed in the extended transparent mode via the MODE register (MDS1,
MDS0 = 11), each channel of the ESCC8 performs fully transparent data transmission
and reception without HDLC framing, i.e. without
q FLAG insertion and deletion
q CRC generation and checking
q Bit-stuffing.
In order to enable fully transparent data transfer, RAC bit in MODE has to be reset and
FF_H has to be written to XAD1, XAD2 and RAH2.
Data transmission is always performed out of XFIFO by directly shifting the contents of
XFIFO via the serial transmit data pin (T×D). Transmission is initiated by setting
CMDR:XTF (08_H); end of transmission is indicated by ISR1:EXE (10_H).
In receive direction, the character last assembled via receive data line (R×D) is available
in RAL1 register. Additionally, in extended transparent mode 1 (MODE: MDS1, MDS0,
ADM = 111), received data is shifted into RFIFO.
This feature can be profitably used e.g. for:
q User specific protocol variations
q Line state monitoring, or
q Test purposes, in particular for monitoring or intentionally generating HDLC protocol
rule violations (e.g. wrong CRC)
Character or octet boundary synchronization can be achieved by using clock mode 1
with an external receive strobe input to pin CD.
2.3.4.5 Cyclic Transmission (Fully Transparent)
If the extended transparent mode is selected, the ESCC8 supports the continuous
transmission of the contents of the transmit FIFO.
After having written 1 to 32 bytes to XFIFO, the command
XREP.XTF.XME
via the CMDR register (bit 7…0 = “00101010” = 2A_H) forces the ESCC8 to repeatedly
transmit the data stored in XFIFO via T×D pin.
The cyclic transmission continues until a reset command (CMDR: XRES) is issued, after
which continuous “1”-s are transmitted.
Note: In DMA-mode the command XREP and XTF has to be written to CMDR.
Semiconductor Group
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