SAB82538 Datasheet, PDF (143/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
IC1, IC0… Interrupt Port Configuration
These bits define the function of the interrupt output stage (pin INT):
IOC1
X
0
1
IOC0
0
1
1
Function
Open drain output
Push/pull output, active low
Push/pull output, active high
Interrupt Status Register 0 (READ)
Value after RESET: 00_H
7
0
ISR0
RME RFS RSC PCE PLLA CDSC RFO RPF (offset: 3A)
All bits are reset when ISR0 is read. Additionally, RME and RPF are reset when the
corresponding interrupt vector is output.
Note: If bit IPC.VIS is set to “1”, interrupt statuses in ISR0 may be flagged although they
are masked via register IMR0. However, these masked interrupt statuses neither
generate an interrupt vector or a signal on INT, nor are visible in register GIS.
RME…
Receive Message End
One complete message of length less than 32 bytes, or the last part of a
frame at least 32 bytes long is stored in the receive FIFO, including the
status byte.
The complete message length can be determined reading the RBCH,
RBCL registers, the number of bytes currently stored in RFIFO is given by
RBC4–0. Additional information is available in the RSTA register.
RFS…
Receive Frame Start
This is an early receiver interrupt activated after the start of a valid frame
has been detected, i.e. after an address match (in operation modes
providing address recognition), or after the opening flag (transparent mode
0) is detected, delayed by two bytes. After an RFS interrupt, the contents of
• RHCR
• RAL1
• RSTA - bits 3-0
are valid and can be read by the CPU.
Semiconductor Group
143