SAB82538 Datasheet, PDF (41/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
version 1 if the optional features of version 2 are not enabled: channel 0 has highest and
channel 7 lowest (channel) priority.
Note: Parallel ports have always lowest priority.
Version 2 upward provides dynamic adjustment of channel priorities by programming the
“highest priority” channel. This is done via the IVA register. Although this register is
unique, it is accessible via all eight channel assigned addresses. Selection of the
“highest priority” channel is simply done with every write access to the IVA register in
conjunction with the channel assigned IVA register address:
IVA Register Address: Highest Priority Channel
38_H
0
78_H
1
B8_H
2
F8_H
3
138_H
4
178_H
5
1B8_H
6
1F8_H
7
The priority level becomes valid with the end of the write access to the IVA register (rising
edge of WR or DS, whichever applies) and remains stable until a new write access to
this register occurs.
Note:
– The sequence of the channels remains unchanged. Only the pointer to the channel
with highest priority is influenced. Therefore, the priority levels of all other channels
follow automatically.
– Parallel ports have always lowest priority.
If the state after Reset shall be unchanged but bits of the IVA register have to be set, the
programming has to be done via IVA register address “38H” (channel 0).
Example:
Initially after Reset, the order of the channels with descending priority from left to right is
as follows:
0 1 2 3 4 5 6 7 pp (pp = parallel port interrupt)
Supposed the IVA register is programmed via the address 138_H (channel 4) the channel
priorities will be reordered as follows:
4 5 6 7 0 1 2 3 pp
Semiconductor Group
41