SAB82538 Datasheet, PDF (91/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.6.3 Bus Configuration
Beside the point-to-point configuration, the ESCC8 effectively supports point-to-
multipoint (pt-mpt or bus) configurations by means of internal idle and collision detection/
collision resolution methods.
In a pt-mpt configuration, comprising a central station (master) and several peripheral
stations (slaves), or in a multimaster configuration (see figure 13), data transmission
can be initiated by each station over a common transmit line (bus). In case more than
one station attempt to transmit data simultaneously (collision), the bus has to be
assigned to one station.
– In HDLC/SDLC mode, a collision-resolution procedure is implemented by the ESCC8.
Bus assignment is based on a priority mechanism with rotating priorities. This allows
each station a bus access within a predetermined maximum time delay (deterministic
CSMA/CD), no matter how many transmitters are connected to the serial bus.
– In BISYNC mode, the collision-resolution is implemented by the microprocessor.
– In ASYNC mode, a bus configuration is not recommended.
Prerequisites for bus operation are:
q NRZ encoding
q OR’ing of data from every transmitter on the bus (this can be realized as a wired-or,
using the TxD open drain capability)
q Feedback of bus information (CxD input).
The bus configuration is selected via the CCR0 register.
Note: Central clock supply for each station is not necessary if both the receive and
transmit clock is recovered by the DPLL (clock modes 3a, 7a). This minimizes the
phase shift between the individual transmit clocks.
The bus mode can be operated independently of the clock mode, e.g. also during clock
mode 1 (receive and transmit strobe).
2.6.3.1 Bus Access Procedure
The idle state of the bus is identified by eight or more consecutive 1’s. When a device
starts transmission of a frame, the bus is recognized to be busy by the other devices at
the moment the first zero is transmitted (e.g. first zero of the opening flag in HDLC
mode).
After the frame has been transmitted, the bus becomes available again (idle).
Note: If the bus is occupied by other transmitters and/or there is no transmit request in
the ESCC8, logical 1 will be continuously transmitted on T×D.
Semiconductor Group
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