SAB82538 Datasheet, PDF (178/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
ASYNC Mode
T4– T2… Device Address Extension
In Interrupt vector mode 2 (bit EDA set) these bits define the value of bits 2
to 4 of the interrupt vector which is sent out on the data bus (D0…D7) during
the interrupt acknowledge cycle.
ROT…
Rotating Interrupt Priority (version 2 upward)
Version 1:
This bit is unused and has to be set to logical “0”.
Version 2:
0 … Fixed Interrupt Priority
The relative order of the interrupt priority level assigned to the
channels is fixed (refer to chapter 2.3.1).
1 … Rotating Interrupt Priority
The interrupt priority level will be adjusted after an interrupt has
been serviced. Together with bit IPC.ROTM the interrupt priority
mode is selected.
IPC.ROTM = 0: The priority level of all 8 serial channels are
adjusted.
IPC.ROTM = 1: The priority level of only 7 channels are adjusted
while one channel is fixed.
EDA…
Extended Device Address
If set, bits 2 to 5 (version 1: bits 2 to 4) of the generated interrupt vector
contain the Device Address Extension T2…T5 (version 1: T2…T4) instead
of the channel number. For detailed information refer to chapter 2.2.3.
Interrupt Port Configuration (READ/WRITE)
Value after RESET: 00_H
7
IPC
VIS ROTM SLA2 SLA1 SLA0 CASM IC1
0
IC0 (039/079/0B9/0F9)
(139/179/1B9/1F9)
Note: Unused bits have to be set to logical “0”.
IPC is accessible via eight channel addresses (039_H to 1F9_H).
VIS…
Masked Interrupts Visible (version 2 upward)
0… Masked interrupt status bits are not visible.
1… Masked interrupt status bits are visible.
Semiconductor Group
178