SAB82538 Datasheet, PDF (131/253 Pages) Infineon Technologies AG – ICs for Communications

Channel Configuration Register 1 (READ/WRITE)
Value after RESET: 00_H
7
CCR1
SFLG GALP GLP ODS ITF/ CM2
OIN
SAB 82538
SAF 82538
HDLC Mode
0
CM0 (offset: 2D)
SFLG…
GALP…
GLP…
Enable Shared Flags
If this bit is set, the closing FLAG of a preceding frame simultaneously
becomes the opening FLAG of the following frame.
Go Active On Loop
Only used if SDLC Loop is enabled.
This bit enables transmission on an SDLC Loop.
1… After detection of the next EOP sequence, the ESCC8 goes to the
Sending On Loop state by changing the seventh 1-bit of the EOP
sequence into a 0, thus creating a Start Flag, and by disconnecting the
T × D pin from the R × D pin. The ESCC8 is now active on loop and
can transmit frames as soon as data is available in the XFIFO. The
time between frames is always filled by sending continuous Flags
(independent from the value of bit CCR1.ITF), thus occupying the
loop.
0… The ESCC8 leaves the Sending On Loop state when the XFIFO is
empty by retransmitting data received on R × D to T × D (with one bit
delay) after the closing flag has been transmitted (thus creating an
EOP sequence).
Go On Loop
Only used if SDLC Loop is enabled.
This command controls entering and leaving the SDLC Loop.
1… The ESCC8 enters the On Loop state after detection of the next EOP
sequence by adding a 1-bit delay between receive and transmit path.
The On Loop state is prerequisite for sending frames on loop.
0… The ESCC8 leaves the On Loop state by suppressing the 1-bit delay
after detection of the next EOP sequence.
Semiconductor Group
131