SAB82538 Datasheet, PDF (126/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
q Extended Transparent Modes 0, 1 - READ Access only:
(Write access has no influence)
RAL1 contains the current data byte assembled from the R × D pin, the HDLC receiver
is by-passed (fully transparent reception without HDLC framing).
In versions 2 upward, this register can be masked by setting the corresponding bits in
the mask register AML to allow extended broadcast address recognition. This feature is
applicable to all operating modes with address recognition.
Receive HDLC Control Register (READ)
7
RHCR
RHCR
0
(offset: 29)
Value of the HDLC control field of the last received frame.
Note: RHCR is copied into RFIFO for every frame.
Contents of RHCR
Mode
Modulo 8 (MCS = 0)
Modulo 128 (MCS = 1)
Auto mode, 1-byte address Control field
(U-frames) (Note 1)
Control field in
(Note 2)
Auto mode, 2-byte address Control field
(U-frames) (Note 1)
Control field in
(Note 2)
Auto mode, 1-byte address Control field
(I-frames) (Note 1)
Control field in
compressed form (Note 3)
Auto mode, 2-byte address
(I-frames) (Note 1)
Non-auto mode,
1-byte address
Non-auto mode,
2-byte address
Transparent
mode 1
Transparent
mode 2
Control field
2^nd byte after flag
3^rd byte after flag
3^rd byte after flag
2^nd byte after flag
Control field in
compressed form (Note 3)
Semiconductor Group
126