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| SAB82538 Datasheet, PDF (128/253 Pages) Infineon Technologies AG – ICs for Communications | |||
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Transmit Byte Count Low (WRITE)
7
XBCL
XBC7
SAB 82538
SAF 82538
HDLC Mode
0
XBC0 (offset: 2A)
Together with XBCH (bits XBC11â¦XBC8) this register is used in DMA Mode only, to
program the length (1â¦4096 bytes) of the next frame to be transmitted. In terms of the
value xbc, programmed in XBC11â¦XBC0 (xbc = 0â¦4095), the length of the block in
number of bytes is:
length = xbc + 1.
This allows the ESCC8 to request the correct amount of DMA cycles after an XTF or XIF
command in CMDR.
Received Byte Count High (READ)
Value after RESET: 000xxxxx
7
0
RBCH DMA NRM CAS OV RBC11
RBC8 (offset: 2B)
see XBCH
DMA, NRM, CASâ¦
These bits represent the read-back value programmed in XBCH
OVâ¦
Counter Overflow
More than 4095 bytes received.
RBC11 â RBC8⦠Receive Byte Count (most significant bits)
Together with RBCL (bits RBC7⦠RBC0) indicate the length of the
received frame.
Semiconductor Group
128
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