SAB82538 Datasheet, PDF (14/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Pin Definitions and Function (cont’d)
Pin No. Symbol
105
DTACK
104
INT
Input (I)
Function
Output (O)
oD
Data Transfer Acknowledge
During a bus cycle (read/write, asynchronous
bus), this signal indicates that ESCC8 is ready for
data transfer. The signal remains active until the
data strobe (DS, RD or WR) and/or the Chip
Select signal (CS) or the Interrupt Acknowledge
(INTA) go inactive. An external resistor has to be
tied to VDD if this function is used.
O/oD
Interrupt Request
INT serves as general interrupt request which
may include all serial mode specific interrupt
sources and the requests of the four universal
ports if programmed. These interrupt sources can
be masked via registers IMR0/1 (for each
channel) and PIMA,B,C,D (universal ports).
Interrupt status is reported via registers GIS
(Global Interrupt Status), ISR0/1 (for each
channel) and PISA,B,C,D (universal ports).
Output characteristics (push-pull active low/high,
open drain) are determined by programming the
IPC register.
In Daisy Chain cascading mode INT signal
generation is only enabled if the Interrupt Enable
input IE1 is active “high”.
INT is reset if
–interrupts are disabled in Daisy Chain
cascading mode (pin IE1 = low),
–no further interrupt is pending,
i.e. all interrupt status bits are reset.
Semiconductor Group
14