SAB82538 Datasheet, PDF (116/253 Pages) Infineon Technologies AG – ICs for Communications

CTS…
WFA…
SAB 82538
SAF 82538
HDLC Mode
Clear To Send State
This bit indicates the state of the CTS pin.
0… CTS is inactive (high)
1… CTS is active (low)
Wait For Acknowledgment (significant in auto-mode only).
Indicates the “Wait for I frame Acknowledgment” status of ESCC8.
Command Register (WRITE)
Value after RESET: 00_H
7
0
CMDR
RMC RHR RNR/ STI XTF XIF XME XRES (offset: 20)
XREP
Note: The maximum time between writing to the CMDR register and the execution of
the command is 2.5 clock cycles. Therefore, if the CPU operates with a very high
clock rate in comparison with the ESCC8's clock, it is recommended that the CEC
bit of the STAR register be checked before writing to the CMDR register to avoid
any loss of commands.
RMC…
Receive Message Complete
Confirmation from CPU to ESCC8 that the current frame or data block has
been fetched following an RPF or RME interrupt, thus the occupied space
in the RFIFO can be released.
Note: In DMA Mode, this command has to be issued after an RME
interrupt, to enable the generation of further receiver DMA requests.
RHR…
Reset HDLC Receiver
All data in the RFIFO and the HDLC receiver is deleted. In auto-mode,
additionally the transmit and receive sequence number counters are reset.
RNR/XREP… Receiver Not Ready / Transmission Repeat
The function of this command depends on the selected operation mode
(MDS1, MDS0, ADM bit in MODE):
• auto mode: RNR
Determines the status of the ESCC8 receiver, i.e. whether a received frame
is acknowledged via an RR or RNR supervisory frame in auto-mode.
0… Receiver Ready (RR)
1… Receiver Not Ready (RNR)
• extended transparent mode 0, 1: XREP
Semiconductor Group
116