SAB82538 Datasheet, PDF (134/253 Pages) Infineon Technologies AG – ICs for Communications

SSEL…
TOE…
RWX…
C32…
DIV…
SAB 82538
SAF 82538
HDLC Mode
Clock Source Select
Selects the clock source in clock modes 0, 2, 3, 6 and 7 (refer to table 5).
TxCLK Output Enable
0… T × CLK pin is input.
1… T × CLK pin is switched to output function if applicable to the selected
clock mode (refer to table 5).
Read/Write Exchange
Valid only in DMA mode. If this bit is set, the
– RD and WR pins are internally exchanged (Siemens/Intel bus interface)
– R/W pin is inverted in polarity (Motorola bus interface)
while any DACK input is active. This feature allows a simple interfacing to
the DMA controller.
Note: The RWX bit of all eight channels is “or”ed.
Enable CRC-32
0… CRC-CCITT is selected.
1… CRC-32 is selected.
Data Inversion
Only valid if NRZ data encoding is selected. Data is transmitted and
received inverted.
Channel Configuration Register 3 (READ/WRITE)
Value after RESET: 00_H
7
0
CCR3 PRE1 PRE0 EPT RADD CRL RCRC XCRC PSD (offset: 2F)
PRE1, PRE0… Number of Preamble Repetition
If Preamble transmission is initiated, the Preamble defined via register PRE
is transmitted
00… 1 times
01… 2 times
10… 4 times
11… 8 times.
Semiconductor Group
134