SAB82538 Datasheet, PDF (40/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Second level: Channel classification
The second level considers the current priority of all channels. Especially for version 2
upward, selection is performed between
– Fixed priority level assignment (version 1: channel 0 has highest and channel 7 lowest
priority; version 2 upward: channel with highest priority is selectable)
– Rotating priority level assignment, all channels (version 2 upward)
– Rotating priority level assignment, 7 channels with the selectable 8th channel fixed to
highest priority (version 2 upward)
The priority level for each interrupt source results from the interrupt group (first level) and
the current priority of the channel (second level). As mentioned above, in ESCC8
version 1 the priorities of the eight serial channel interrupts are fixed, with channel 0
having always the highest, channel 7 the lowest priority.
For ESCC8 Version 2 upward the priority levels are fixed or adjusted after an interrupt
has been serviced, namely, the priorities are rotated cyclically so that the channel last
serviced is assigned the lowest priority of all. Port interrupts are not affected by the
priority rotation, and are always assigned lowest priority. The interrupt priority rotation
mode is selectable via two control bits IVA.ROT and IPC.ROTM.
When an interrupt has been generated updating of all interrupt priorities takes place after
the generated interrupt has been acknowledged, i.e.
– For interrupts that are unambiguously determined by the contents of the interrupt
vector, after the end of a complete INTAQ cycle (1 or 2 pulse, whichever applies).
Such interrupts are: Receive Data Interrupts RPF, RME/TCD and Transmit Data
Interrupt XPR for all channels, or,
– Whenever the interrupt status which caused the currently active interrupt to be
generated (i.e. one with currently the highest priority among all unmasked pending
interrupts) is cleared by reading an interrupt status register ISR0_0...7, ISR1_0...7 or
PISA...D. Reading other interrupt status registers may clear other pending interrupts
(if any).
The following interrupt priority modes apply only to the channel identification (second
level).
Interrupt priority mode 1: Fixed priority
After Reset the ESCC8 operates with fixed priority, i.e. the relative order of the priority
levels assigned to the channels is fixed and there is no change after an interrupt has
been serviced.
Apart from the change in the format of the interrupt vector (version 2 upward: channel 7
interrupts are separated from the parallel ports interrupts) version 2 is compatible with
Semiconductor Group
40