SAB82538 Datasheet, PDF (140/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
CII…
Channel Interrupt Indication
Set if at least one interrupt source of any channel is active.
CN2 – CN0… Channel Number (0..7)
If at least one interrupt source is active (bit CII is set), these bits point to the
channel with currently highest source priority. Refer to chapter 2.2.3 for
detailed description of the priority structure.
Contents of register GIS are frozen after every input acknowledge cycle.
– after the first read access to GIS after the interrupt vector has been output,
– after every read access to anyone of the channel assigned interrupt status registers,
– during every INTA cycle.
Interrupt Vector Address (WRITE)
Value after RESET: 00_H
7
IVA T7 T6 T5 T4 T3
0
T2 ROT EDA (038/078/0B8/0F8)
(138/178/1B8/1F8)
Note: Unused bits have to be set to logical “0”.
IVA is accessible via eight channel addresses (38_H to 1F8_H).
Version 2 upward provides dynamic adjustment of channel priorities by programming the
“highest priority channel”. Selection of the “highest priority channel” is done with every
write access to IVA in conjunction with the channel assigned IVA register address:
IVA Register Address: Highest Priority Channel
38_H
0
78_H
1
B8_H
2
F8_H
3
138_H
4
178H
5
1B8H
6
1F8H
7
The priority level becomes valid with the end of the write access to the IVA register (rising
edge of WR or DS, whichever applies) and remains stable until a new write access to
this register occurs.
Semiconductor Group
140