SAB82538 Datasheet, PDF (85/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
Depending to the value programmed via those bits, the receive/transmit window (time-
slot) starts with a delay of 1 (minimum delay) up to 512 clock periods following the frame
synchronization signal and is active for the number of clock periods programmed via
RCCR, XCCR (number of bits to be received/transmitted within a time-slot) as shown in
figure 35.
If bit CCR2.TOE is set, the transmit time-slot is indicated by a control signal via TxCLK,
which is set to “low” during the transmit window.
Note: In HDLC/SDLC Extended Transparent modes above windows provide character
synchronization (byte aligned). In extended transparent mode the width of the
time-slots has to be nx8 bit. In all other modes they can be used to define windows
down to a minimum length of one bit.
Figure 35
Location of Time-Slots
Clock Mode 6 (OSC - Rec. Clock from DPLL)
This clock mode is identical to clock mode 2 except that the clock for the BRG is
delivered by the OSC and must not be supplied externally.
Clock Mode 7 (OSC - Rec. and Trm. Clock from DPLL)
Similar to clock mode 3, but BRG clock is provided by OSC.
Semiconductor Group
85