SAB82538 Datasheet, PDF (141/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
T7 – T6…
Device Address
These bits define the value of bits 6 and 7 of the interrupt vector which is
sent out on the data bus (D0… D7) during the interrupt acknowledge cycle.
T5…
Device Address
Version 1: Device Address
This bit defines the value of bit 5 of the interrupt vector which is
sent out on the data bus (D0… D7) during the interrupt
acknowledge cycle.
Version 2: Device Address Extension
In Interrupt vector mode 2 (bit EDA set) this bit defines the value
of bit 5 of the interrupt vector which is sent out on the data bus
(D0… D7) during the interrupt acknowledge cycle.
T4 – T2…
Device Address Extension
In Interrupt vector mode 2 (bit EDA set) these bits define the value of bits 2
to 4 of the interrupt vector which is sent out on the data bus (D0… D7)
during the interrupt acknowledge cycle.
ROT…
Rotating Interrupt Priority (version 2 upward)
Version 1:
This bit is unused and has to be set to logical “0”.
Version 2:
0 … Fixed Interrupt Priority
The relative order of the interrupt priority level assigned to
the channels is fixed (refer to chapter 2.3.1).
1 … Rotating Interrupt Priority
The interrupt priority level will be adjusted after an interrupt
has been serviced. Together with bit IPC.ROTM the
interrupt priority mode is selected.
IPC.ROTM = 0: The priority level of all 8 serial channels are
adjusted.
IPC.ROTM = 1: The priority level of only 7 channels are
adjusted while one channel is fixed.
EDA…
Extended Device Address
If set, bits 2 to 5 (version 1: bits 2 to 4) of the generated interrupt vector
contain the Device Address Extension T2..T5 (version 1: T2..T4) instead of
the channel number. For detailed information refer to chapter 2.2.3.
Semiconductor Group
141