SAB82538 Datasheet, PDF (133/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
HDLC Mode
Channel Configuration Register 2 (READ/WRITE)
Value after RESET: 00_H
The meaning of the individual bits in CCR2 depends on the clock mode selected via
CCR1 as follows:
7
0
CCR2
clock mode SOC1 SOC0 0 SSEL 0 RWX C32
0a, 1
clock mode BR9 BR8 BDF SSEL TOE RWX C32
0b,2,3,6,7
DIV (offset: 2E)
DIV
clock mode SOC1 SOC0 0
4
0 TOE RWX C32 DIV
clock mode SOC1 SOC0 XCS0 RCS0 TOE RWX C32 DIV
5
Note: Unused bits have to be set to logical “0”.
SOC1, SOC0… Special Output Control
In a bus configuration (selected via CCR0), defines the function of pin RTS
as follows:
0X… RTS output is activated during transmission of a frame.
10… RTS output is always high (RTS disabled).
11… RTS indicates the reception of a data frame (active low).
In a point-to-point configuration (selected via CCR0) the T × D and R × D
pins may be flipped
0X… data is transmitted on T × D, received on R × D (normal case).
1X… data is transmitted on R × D, received on T × D.
BR9, BR8… Baud Rate, Bit 9-8
High order bits, see description of BGR register.
XCS0, RCS0… Transmit/Receive Clock Shift, Bit 0
Together with bits XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR) the clock
shift relative to the frame synchronization signal of the Transmit (Receive)
time-slot can be adjusted. A clock shift of 0… 7 bits is programmable.
BDF…
Baud Rate Division Factor
0… The division factor of the baud rate generator is set to 1 (constant).
1… The division factor is determined by BR9 - BR0 bits in CCR2 and BRG
registers.
Semiconductor Group
133