SAB82538 Datasheet, PDF (75/253 Pages) Infineon Technologies AG – ICs for Communications

SAB 82538
SAF 82538
2.4.3 Data Transmission
The selection of asynchronous or isochronous operation has no further influence on the
transmitter. The bit clock rate is solely a dividing factor for the selected clock source.
Transmission of the contents of XFIFO starts after the XF command is issued (the LSB
is sent out first). Further data is requested by interrupt (XPR) or DMA. The character
frame for each character, consisting of Start Bit, the character itself with defined
character length, optionally generated parity bit and Stop Bit(s) is assembled.
After finishing transmission (indicated by the “All Sent” interrupt), IDLE (logical “1”) is
transmitted on T×D.
Additionally, the CTS signal may be used to control data transmission.
2.4.4 Special Features
2.4.4.1 Break Detection/Generation
Break generation: On issuing the XBRK command (register DAFO), the T×D pin is
immediately forced to physical “0” level with the first following clock edge, and released
with the first clock edge after this command has been reset.
Break detection: The ESCC8 recognizes the Break condition upon receiving
consecutive (physical) “0”s for the defined character length, the optional parity and the
selected number of Stop Bits (“zero” character and framing error). The “zero” character
is not pushed to RFIFO. If enabled, the BRK interrupt is generated.
The Break condition will be present until a “1” is received which is indicated by the Break
Terminated interrupt (BRKT).
2.4.4.2 Flow Control by XON/XOFF (version 2 upward)
Programmable XON and XOFF
Two eight-bit control registers (XON, XOFF) contain the programmable values for XON
and XOFF characters. The number of significant bits in a register is determined by the
programmed character length (right justified).
Two programmable eight-bit registers MXN and MXF serve as mask registers for the
characters in XON and XOFF, respectively:
A “1” in a mask register has the effect that no comparison is performed between the
corresponding bits in the received characters (“don’t cares”) and the XON and the XOFF
register. At RESET, the mask registers are zeroed, i.e. all bit positions are compared.
Semiconductor Group
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