SAB82538 Datasheet, PDF (118/253 Pages) Infineon Technologies AG – ICs for Communications

Preamble Register (WRITE)
Value after RESET: 00_H
7
PRE
PR7
SAB 82538
SAF 82538
HDLC Mode
0
PR0 (offset: 21)
This register defines the pattern which is sent out during preamble transmission (refer to
register CCR3).
Note: It should be taken into consideration that Zero Bit Insertion is disabled during
preamble transmission.
Receive Status Register (READ)
7
RSTA
VFR RDO CRC RAB HA1 HA0 C/R
0
LA (offset: 21)
Note: RSTA relates to the last received HDLC frame; it is copied into RFIFO when end-
of-frame is recognized (last byte of each stored frame).
VFR…
Valid Frame
Determines whether a valid frame has been received.
1… valid
0… invalid
An invalid frame is either
– a frame which is not an integer number of 8 bits (n × 8 bits) in length
(e.g. 25 bits), or
– a frame which is too short taking into account the operation mode
selected via MODE (MDS1, MDS0, ADM) and the selected CRC
algorithm (CCR2.C32) and the selection of receive CRC ON/OFF
(CCR3.RCRC) as follows:
• Auto-/Non-Auto-Mode (16 bit Address),
RCRC = 0 : 4 bytes (CRC-CCITT) or 6 (CRC-32)
• Auto-/Non-Auto-Mode (16 bit Address),
RCRC = 1 : 3-4 bytes (CRC-CCITT) or 3-6 (CRC-32)
• Auto-/Non-Auto-Mode (8 bit Address),
RCRC = 0 : 3 bytes (CRC-CCITT) or 5 (CRC-32)
• Auto-/Non-Auto-Mode (8 bit Address),
RCRC = 1 : 2-3 bytes (CRC-CCITT) or 2-5 (CRC-32)
• Transparent Mode 1: 3 bytes (CRC-CCITT) or 5 (CRC-32)
• Transparent Mode 0: 2 bytes (CRC-CCITT) or 4 (CRC-32)
Note: Shorter frames are not reported.
Semiconductor Group
118